1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a function of refreshing stored data.
2. Description of the Related Art
A class of semiconductor memory devices such as dynamic random-access memories (DRAMs) store each data bit in the form of a charge on a very small capacitor. Because of the presence of leakage current from capacitors, the stored data cannot be retained indefinitely. The lost capacitor charge must be restored at appropriate intervals by rewriting the same data. This restoration operation is called “refresh.”
Existing semiconductor memory devices have an internal address counter to generate refresh address, which is typically a binary counter to produce binary address. This is, however, not always an efficient way. In the case the actual memory size cannot be represented in the form of 2n, the address counter would produce useless address values after it has reached the maximum real memory address.
One technique to overcome the above inefficiency in refresh address generation is to use shift registers. Specifically, the semiconductor memory device contains shift registers corresponding to individual word lines of each memory cell array. In refresh cycles, those shift registers successively generate a series of refresh addresses, thus scanning all word lines efficiently. (See, for example, the Japanese Patent Application Publication No.2000-311487, pages 4 and 5, FIGS. 1 to 3.)
We should, however, note that the conventional semiconductor memory devices described above are designed to distribute common control signals to all shift registers when updating refresh address. Since the number of shift registers increases in proportion to memory capacity, the power consumption in driving those control signals would be a problem.